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RTL, SOC֤
RTLԱϤverilog
֤ԱSOC֤, BFMд, testcaseд
һunix, perl, shell scripts, cvs
Ҫ:
     RTLʦϤVERILOG, һСĿ.
     ֤ʦҪϤԭ, йǶʽϵͳͿ
     һϤunixͿ
нҵûҵ  Թ? 
ļ weichyan@163.com
վ
Ӣĸһݰ, ҪӢĵ
ͷverificationԭʼrequirements JD:
ҾҪ̫, ĳ
SOC Verification Engineer 
 
Requirement:
*       Familiar with ASIC/SOC verification flow.
*       Proficient in Verilog, C/C++, Unix-Shell scripting/Perl scripting.
*       Familiar with HDL-Lint , Gate-level simulations, Equivalence checking.
*       Minimum of MSEE or MSCS
*       3+ Years experience
 
Job description:
*       Maintain SOC level test environment for regression automation.
*       Maintain design code revision control, like CVS.
*       Maintain flow for quality RTL deliverables for synthesis, verification, DFT, coding style and naming scheme  by use of lint programs.
*       Maintain flow for RTL Vs. Gate-level netlist Equivalence checking.
*       Ideal person will play a support role in the overall verification of SOC design.
 

